FIGS. 1-2 depict a small portion of a conventional spin transfer torque random access memory (STT-RAM) 1. FIG. 1 depicts a circuit diagram of the portion of the conventional STT-RAM 1, while FIG. 2 depicts a cross-sectional view of the portion of the conventional STT-RAM 1. The conventional STT-RAM 1 includes a conventional magnetic storage cell 10 including a conventional magnetic element 12 and a conventional selection device 14 that is preferably an isolation transistor 14, word line 24, source line 26, and bit line 28. The source line 26 is shown oriented perpendicular to the bit line 28. However, the source line 26 is typically either parallel or perpendicular to the bit line 28, depending on specific architecture used for the conventional STT-RAM 1.
The conventional magnetic element 12 may be a magnetic tunneling junction (MTJ) or other analogous magnetic element and is configured to be changeable between resistance states by driving a current through the conventional magnetic element 12. The current changes state of the conventional magnetic element 12 using the spin transfer torque switching effect. Typically, this is achieved by ensuring that the conventional magnetic element 12 has a sufficiently small cross-sectional area and that the layers of the magnetic element, such as pinned, spacer and free layer (not separately shown) have particular thicknesses. When the current density is sufficient, the current carriers driven through the conventional magnetic element 12 may impart sufficient torque to change the state of the conventional magnetic element 12. When a write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is driven in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
The conventional selection device 14 is typically a conventional planar transistor, such as a planar MOSFET. The conventional planar transistor 14 includes a conventional source 16, a conventional gate 18, a conventional drain 20, and a conventional gate oxide 22. The conventional source 16 and conventional drain 20 are typically N-doped and reside in a P-well 15 formed within the substrate 13. The conventional planar transistor 14 is termed a “planar” transistor because the conventional gate oxide 22 separating the conventional gate 18 from the P-well 15 is substantially planar. When a threshold voltage is applied to the conventional gate 18 through the conventional word line 24 current can flow between the conventional source 16 and the conventional drain 20. This current may be used in programming the conventional magnetic element 12 via spin transfer.
In order to program the conventional storage cell 10, the conventional word line 24 and thus the conventional planar transistor 14 are activated. A current is driven between the conventional source line 26 and the conventional bit line 28 by supplying a high voltage to the conventional bit line 28 and a low voltage, such as ground, to the conventional source line 26, or vice versa. For a read operation, the bit line 28 and the word line 24 are activated. Consequently, the conventional planar transistor 14 is turned on. A read current is driven through the conventional magnetic element 12. In order to ensure that the conventional storage cell 10 is not written during a read operation, the read current is typically less than the write current. Thus, the conventional magnetic storage cell 10 can be programmed and read.
Although the conventional STT-RAM 1 functions, one of ordinary skill in the art will recognize that there are drawbacks. It is desirable for the conventional STT-RAM 1 to be integrated at higher densities. For the conventional STT-RAM 1 to operate at sufficiently high speeds, it is desirable for the current pulse used to be low. For example, the switching current pulse may be desired to have a width ten nanoseconds or less. However, one of ordinary skill in the art will recognize that the required switching current increases rapidly, particularly for pulse widths below ten nanoseconds. The magnitude of the current through the conventional magnetic element 12 may be limited by the amount of current that can pass through the conventional planar transistor 14. The current passing capability of the conventional planar transistor 14 is proportional to the width of the gate 18. The gate width is measured perpendicular to the cross-section shown in FIG. 2. Thus, the gate width is length of the gate 18 out of the plane of the page in FIG. 2. As the switching current increases, the conventional planar transistor 14 has a larger gate width to support the current. Consequently, it is difficult to fabricate higher density cells 10.
The conventional planar transistor 14 may give rise to other issues as the conventional STT-RAM 1 scales to higher densities. As the gate length, l, scales to smaller sizes, for example from ten microns to fifty nanometers and beyond, the supply voltage decreases. The supply voltage is decreased to account for the reduction in the thickness of the gate oxide 22 at smaller sizes. In addition, the relative transistor leakage power level increases as the technology scales down from 0.25 micron to forty-five nm. For conventional STT-RAM 1 applications, the power leakage generally reaches an unacceptable level for devices having a critical dimension, or gate length, of forty-five nm or less. To compensate for the power leakage, the threshold voltage (Vt) of the conventional planar transistor 14 used for memory chips or embedded memories can be increased. This is effective in reducing leakage power in the off state. However, a slightly high Vt may significantly reduce the saturation current of the conventional planar transistor 14. In a conventional STT-RAM cell 10, such a reduction in saturation current means that the write current that may pass through the magnetic element 12 is reduced. The reduction in saturation current may be compensated by using a conventional planar transistor 14 having a much larger gate width. However, a large conventional planar transistor 14 causes the size of the conventional cell 10 to increase. In addition, as discussed above, the supply voltage rapidly decreases as the transistor 14 technology scales down. The transistor drain to source saturation current, the same current that is allowed to pass through the conventional magnetic element 12, depends on the value of the gate voltage (Vg). A reduction of Vg, for example from 1.5 v to 1.0 v, reduces saturation current to ⅕ of its original value. Consequently, as the supply voltage scales down, the gate width of the conventional planar transistor 14 may be scaled up to supply a sufficient write current for switching the state of the conventional magnetic element 12. Consequently, the conventional cell 10 utilizing the conventional planar transistor 14 may be difficult to scale to higher densities.
Accordingly, what is desired is a method and system for providing and utilizing memory cells employing spin transfer based switching that may be extended to higher densities. The present invention addresses such a need.